1. Field of the Invention
The present invention relates generally to digital circuitry for generating control signals to logic devices. In particular, the present invention relates to a control circuit using delay lines to generate clock and control signals during a clock cycle of the system clock.
2. Description of the Prior Art
Presently, a scan converter is used to convert a scanned image from missile seeker into a planner image for viewing on a video monitor. The conversion of the scanned image by the scan converter involves a process whereby each pixel of the image is weighted using algorithms selected by the user.
A weight is defined for each pixel in each sample which is the product of the weight for the number of overlapping samples and the weight which represents the percentage of the pixel covered by a detector for pixels near the edge of the detector. These weights are stored in a look-up table format in memory. As samples are taken, the weights are extracted from the look-up table and multiplied with a new pixel. Since different scan samples can overlap, the new pixel is summed with the previously scanned pixel to generate the final pixel value for a particular location.
The scan converter uses a plurality of logic elements including PROMs, a dual port RAM, a multiplier/accumulator and comparators to process the incoming pixel data. Each of the logic elements requires the generation of control and timing signal to perform its associated function.
Control circuits normally generate control and timing when the rising edge of the clock signal occurs. However, some of the control and timing signals for the scan converter require a delay after the rising edge of the clock pulse of the system clock signal. For the scan converter the system clock signal has a frequency of 50 megahertz with a period of 40 nanoseconds. A number of the control and timing signals for the logic elements of the scan converter require either a five nanosecond or a fifteen nanosecond delay from the rising edges of the 50 megahertz system clock signal. This, in turn, would normally require the use of a 200 megahertz clock signal generator with the scan converter to generate these five nanosecond or fifteen nanosecond delays for a number of the timing control signals used within the scan converter. However, it is desirable to generate these five nanosecond and fifteen nanosecond delays without adding an additional clock signal generator to the scan converter.